1. Field of the Invention
The present invention relates to a method, system, and program for determining the system configuration and, in particular, determining the available devices in the system from self-defining configuration information provided with each device.
2. Description of the Related Art
The computer architecture of certain computer systems, such as server class machines, includes a configuration processor that during initialization, such as a power-on self test (POST), performs a series of diagnostic tests to query the system components to determine the system configuration. In personal computers, this process is performed by a Basic Input/Output System (BIOS) code that determines the devices in the system. Devices that may be included in a computer system include a configuration processor that performs configuration and initialization operations during system initialization, one or more central processing units (CPUs), one or more riser cards having attached memory cards, such as dual in-line memory modules (DIMMs), and other components. Typically each card or field replaceable unit (FRU) in the system has its own EEPROM chip that includes vital product data (VPD) for the device. All the FRUs in the system communicate over a planar bus interface, such as the I2C bus interface which provides a serial protocol for passing information on the bus.
In some prior art systems, the configuration processor is coded with a configuration of the devices on the planar or backplane I2C bus and any further devices that may be connected at different levels to those devices. The code for the configuration processor may be maintained in a programmable memory, such as a PROM or EEPROM. For instance, a riser card on the planar I2C bus may include one or more of its own I2C busses. DIMM cards having their own EEPROMs with configuration information may be attached to one or more I2C bus interfaces inside the riser card. The configuration processor code would include address information on all current system components on the planar I2C bus and all components on any buses at different levels within a card, i.e., on I2C busses within a card. During configuration, the configuration processor can then send read configuration data requests to each component to confirm that the devices are operational. One problem with coding the specific system configuration into the configuration code is that changes may be made to the system, such as inserting a new riser card having a different DIMM configuration. In such case, before the system can function with the new configuration, the configuration processor code would have to be updated to reflect this new configuration. This complicates altering the system configuration because any change will have to be accompanied by a change to the configuration processor code by modifying the configuration memory, e.g., PROM, EEPROM.
Some prior art systems encode in the configuration processor code the address of all possible components that may be attached to the system. The configuration processor will then send read configuration data requests to all possible attached systems, regardless of whether those devices are in the system, and wait for a response. Those devices that respond are included in the initialization and system configuration and those devices that do not respond are assumed to be absent from the system. This approach has the advantage over the previous approach in that any changes to the FRUs in the system, such as adding or removing DIMM cards, will not require an accompanying update to the configuration code as such changes will be detected when the configuration processor queries all possible available components.
However, one disadvantage of having the configuration processor check all possible device addresses is that such an operation can substantially delay the configuration and initialization processes because the configuration processor must wait for responses from all possible devices in the system. Further, if the system is reconfigured in a manner that is not in the possible configurations indicated in the configuration code, then the configuration processor will not detect the new arrangement unless the configuration code is updated with the capabilities of the new architecture. For instance, if the configuration code indicated that at most there may be 32 DIMM cards on four I2C busses within a riser card and a card was added that would permit 64 DIMM cards on eight different I2C bus interfaces, then the configuration code would have to be updated to reflect all possible 64 DIMM addresses where cards may be added.
Thus, there is a need in the art for an improved technique for configuring a system to determine available components.
To overcome the limitations in the prior art described above, preferred embodiments disclose a method, system, and program for determining the configuration of a computer system having a planar board, a planar bus and attached planar devices. A read operation is performed on planar configuration memory indicating addresses for each planar device capable of being attached to the planar board. A read command is then sent to the address of each planar device indicated in the planar configuration memory to determine if each planar device is available. A configuration memory for each available planar device is read to determine configuration information and if there are addresses of attached devices accessible through one planar device. A read command is then sent to the address of each attached device indicated in the configuration memory of the planar device to determine configuration information for each attached device and if there are further attached devices accessible through the attached device. A read command is sent to the address of any attached device indicated in any configuration memory to determine configuration information and whether there are any further attached devices and accompanying configuration memories to consider.
In further embodiments, at least one device includes an internal bus having attached devices accessible through the internal bus. The configuration memory of the device indicates an address of the attached devices on the internal bus. In such case, read commands are sent to the attached devices using the internal bus address information in the configuration memory of the device including the internal bus.
In still further embodiments, the configuration information includes product information. Address and product information read from the configuration memory of the devices in the system is stored in memory for use during computer operations.
Preferred embodiments provide a computer architecture that optimizes the system initialization process and determination of the system configuration. Preferred embodiments provide a planar configuration processor on the planar bus interface that indicates each possible device on the planar board. Any devices attached to the planar devices or any devices attached to devices that are themselves attached to a planar device or attached device have a configuration memory that includes product information on the device and address information for any devices attached to the device. During initialization, the configuration processor can determine the configuration by determining any devices attached at a particular level and then querying the configuration memories for those attached devices to find the addresses of any further attached devices. In this way, each level of the system configuration is determined from configuration memories including information on the devices at a particular level.
The advantage of the preferred embodiments is that if a device and its attached devices are replaced with a device having a different configuration, this new configuration can be detected from the configuration memory for the new device during system initialization. Furthermore, with the preferred embodiments, the configuration processor only sends read commands to existing devices as the address of devices in the system are determined from configuration memories on each device that include self-defining information on the device and actual attached devices. In this way, the preferred configuration memory architecture minimizes the number of read operations needed to dynamically determine system configuration operations.